|A Man Crying Alone In The
|Posted: Sat Dec 17, 2005 8:31 pm Post subject: Re: Forth chip patents
John Doty wrote:
|Bernd Paysan wrote:
Note that practically all early mainframe CPUs could fetch more than one
instruction in a go. The CDC6600 e.g. could fetch four 15 bit instructions
in one go (60 bit words), and that was late 50s.
My VLIW SMP MPP FORTH protocol and hardware model ( theory) ALSO use
..... a balance of four 16-bit primitives align fetched on 64-bits
boundaries, ( in my near optimal VLIW SMP MPP FORTH parallel chip
model, gand unification parallel ( multi core) chip theory)
Three 16-bit/5-bit packed instructions may be encoded within a 16-bit
instructions, the 5-bit encoded branches are hard-wired as 64-bit
relative offests in a simple relatively addressed 16-bit memory
architecture. ( 64k of 64-bit/four-16-bit words are /mostly/ addressed
ONLY using 16-bit relative branches ( of 64-bit offsets. ), indirect
calls, CLASS-BASE METHOD, CLASS-LOCAL-METHOD protocal primitive (
machine?) instructions excluded )
OBVIOUSLY, the 5-bit packed code function as similar to a Transputer's
'Type F' instruction but 31 ( thirty -one) indirectly vectored types
instead of simply one 'F' instruction, ( type of )).
Von Neumann's machine at the Institute for Advanced Study packed two 20
bit instructions into a 40 bit word. Memory was 40 electrostatic storage
tubes, each storing 1k bit, accessed in parallel. Placed in service in 1952.
John Doty, Noqsi Aerospace, Ltd.
His diagnosis of the hostility ... reflects the willful blindness of the
invader who assures himself that the natives are only made unfriendly by
some other provocation than his own. -Barbara W. Tuchman